Circuitry may be used in memory systems to delay received commands and addresses for a number of clock cycles. For example, a memory array may include memory cells arranged in rows and columns. A row address, and accompanying row address strobe signal (/RAS) may be coupled to the array and the corresponding row activated. A column address, and accompanying column address strobe signal (/CAS) may be coupled to the array to read data out of (or write data to) a particular column of the activated row. It may take time for the selected row to be activated, and the column address strobe signal should not be received until the activation is complete. Accordingly, it may be desirable to delay the column address strobe signal, the column address, or both, from the time they are received by the memory system to a later time when they may be applied to the memory array with increased confidence that the row will be activated.
Accordingly, an example of a pipeline 100 for delaying a command is shown in FIG. 1. The pipeline 100 includes fifteen flip-flops 110a-110o. Each of the flip-flops 110a-110o includes an input node, an output node, a first and second clock node, and a reset node. A command, CmdQd, may be received at the input node of the flip-flop 110a and latched using a clock signal T1Clk applied to the flip-flop 110a at the first clock node. The complementary clock signal T1Clkf may be applied to the flip-flop 110a at the second clock node, and a reset signal RST applied to the flip-flop 110a at the reset node to control operation of the flip-flop 110a. Accordingly the flip-flop 110a may output Cmd<1>, a delayed version of the signal CmdQd.
The Cmd<1> signal may be input to the next flip-flop 110b, controlled using a local clock signal LCK. The flip-flops 110b-110o are controlled such that each flip-flop stores the received command signal for one cycle of the LCK signal. In this manner, the command is stored in the flip-flop 110b during one LCK cycle, then stored in the flip-flop 110c during a next LCK cycle, then stored in the flip-flop 110d during a next LCK cycle, and so on. Using the fifteen flip-flops 110a-110o shown in FIG. 1, the final output Cmd<15> may be delayed fifteen clock cycles from the original input CmdQd, satisfying a latency specification of 15.
In this manner, command latency may be achieved by providing a pipeline having a number of flip-flop stages equal to the latency desired.